As illustrated in example FIG. 1A, generally, a LDMOS transistor may include two n-type drift regions (Ndrifts) 20, 22 formed in high-voltage p-type well (HPWELL) 10.
As illustrated in example FIG. 1B, shallow trench isolations (STIs) 30, 32, 34 and 36 may then be formed in predetermined regions in HPWELL 10 and Ndrifts 20, 22. Gate insulating film 40 and gate 42 may then be sequentially formed on and/or over HPWELL 10.
As illustrated in example FIG. 1C, high-concentration n+-type source/drain extension regions 50, 52 may be then be formed in Ndrifts 20, 22, respectively. Thereafter, through a contact formation process, contacts 60, 62 are formed on and/or over source/drain extension regions 50, 52 formed in Ndrifts 20, 22, respectively.
STIs 32, 34 are provided in order to improve a breakdown voltage of Ndrifts 20, 22 that surround source/drain extension regions 50, 52 in the high voltage transistors. However, an electric field applied in a channel region between source/drain extension regions 50, 52 may be higher than an electric field applied between Ndrifts 20, 22 and the substrate. Accordingly, gate 42 must have a length not less than a predetermined level in order to improve the breakdown voltage between the source and the drain. Consequently, highly integration devices cannot be obtained.